This invention relates generally to data communications systems in which a transmitter sends a stream of user data across a communications loop to a receiver.
More particularly, this invention pertains to devices and methods for facilitating the process of acquiring and maintaining timing between data transmitters and receivers where an equalizer is used to adapt the receiver to overcome distortion in the user data signal caused by the communications loop.
In conventional digital communication systems, a stream of digital user data is sent from a transmitter to a receiver across one or more pairs of wires. In practice, a wire pair, sometimes referred to as a communications loop, can have different electrical characteristics that cause transmission delays, distortion of the transmitted data signal, and narrowing of the channel bandwidth. The data communications process in these systems requires that there be a timing synchronization between the transmitter and receiver. The problem of acquiring and maintaining this timing is a difficult one, particularly in systems where the edge of the received signal band is significantly attenuated or distorted due to the electrical characteristics of the loop.
Conventional digital communications receivers often use timing loop circuits of the type shown in FIG. 1 to recover timing from a received random digital signal. The timing loop shown in FIG. 1 is sometimes referred to as an “early-late” timing loop because it generates a phase error signal which is based on samples from the received signal that are taken slightly earlier and slightly later than the desired sample. The timing loop includes a data sampler having an input coupled to receive and sample the received digital signal and an output connected to a phase detector. The phase detector provides a phase error output signal corresponding to a difference between the mean squared values of the late samples and the early samples. The timing loop attempts to force the difference between the mean squared early samples and the mean squared late samples to be equal to zero, i.e., a zero phase error. To achieve this, the timing loop of FIG. 1 will generate a filtered error signal to adjust the frequency of a voltage controlled oscillator (VCO) until zero phase error is reached.
The rationale for using such an “early-late” timing loop is shown in the “eye” diagram of FIG. 2. Preferably, the timing loop will operate such that the “on-time” sample occurs at the widest opening of the eye diagram. In the example shown in FIG. 2, however, the on-time sample is too far to the left. It can be seen in this example that, on the average, the square of the early sample will be smaller than the square of the late sample. This will result in a negative phase error, which will reduce the VCO frequency and move the on-time sample to the right of the diagram.
A particular difficulty arises when the eye diagram like the one shown in FIG. 2 becomes distorted because of inter-symbol interference produced by the communications loop through which the signal must travel. When this occurs, there may not be a clear “eye” opening, and it becomes very difficult to distinguish between the early sample and the late sample.
Conventional communications receivers use linear equalizers to undo the effects of signal distortion caused by the communications loop. The linear equalizer must “train” initially to time synchronize with the incoming data stream. The training process results in setting the value of coefficients in the equalizer. In conventional receivers, both the equalizer and the timing loop can affect the transmitter/receiver timing relationship. During operation of the receiver, the timing loop is attempting to keep the data sampling time in the same relative position. The transmitter is sending data samples at a rate determined by its internal time base. The timing loop tries to adjust its time base so that it exactly matches the time base used in the transmitter. When the transmitter and receiver first start up, they are not time locked to each other. As the training process proceeds, eventually the transmitter and receiver become time locked where they are sampling at the same frequency.
As noted above, a conventional timing loop is trying to drive the receiver timing to a position where the timing error is zero. If the equalizer adjusts timing by, for example, one quarter of a sample then the timing loop will attempt to adjust to that change. If, as is done in conventional receivers, the timing error is taken at the output of the equalizer, an operational conflict is created between the timing loop and the equalizer. In some cases, such as when a communications system is operating continuously over an extended period of time, the equalizer will drift out of its operational range and cause a disruption in communications between the transmitter and receiver. In an attempt to overcome this problem, some in the prior art have taken the timing signal before the equalizer, using an unfiltered signal. This approach has not been effective in that there can be excessive noise in the timing loop due to distortion, resulting in performance loss.
What is needed, then, is a data communications receiver that includes an improved timing loop that acquires and maintains timing between data transmitters and receivers where an equalizer is used to adapt the receiver to overcome distortion in the user data signal caused by the communications loop.